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HB52R1289E22-a6b/b6b 1 gb registered sdram dimm 128-mword 72-bit, 100 mhz memory bus, 2-bank mod- ule (36 pcs of 64 m 4 components) pc100 sdram ade-203-1087 (z) preliminary rev. 0.0 jul. 14, 1999 description the HB52R1289E22 belongs to 8-byte dimm (dual in-line memory module) family, and has been devel- oped as an optimized main memory solution for 8-byte processor applications. the HB52R1289E22 is a 64m 72 2-bank synchronous dynamic ram module, mounted 36 pieces of 256-mbit sdram (hm5225405btb) sealed in tcp package, 1 piece of pll clock driver, 3 pieces register driver and 1 piece of serial eeprom (2-kbit) for presence detect (pd). an outline of the HB52R1289E22 is 168-pin socket type package (dual lead out). therefore, the HB52R1289E22 makes high density mounting possible without surface mount technology. the HB52R1289E22 provides common data inputs and outputs. decoupling ca- pacitors are mounted beside tcp on the module board. note: do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. features ? fully compatible with: jedec standard outline 8-byte dimm : intel pcb reference design (rev. 1.2) ? 168-pin socket type package (dual lead out) outline: 133.37 mm (length) 38.10 mm (height) 4.80 mm (thickness) lead pitch: 1.27 mm ? 3.3 v power supply ? clock frequency: 100 mhz (max) ? lvttl interface ? data bus width: 72 ecc ? single pulsed ras ? 4 banks can operates simultaneously and independently ? burst read/write operation and burst read/single write operation capability ? programmable burst length: 1/2/4/8 ? 2 variations of burst sequence sequential a
HB52R1289E22-a6b/b6b 2 interleave ? programmable ce latency: 3/4 (HB52R1289E22-a6b) : 4 (HB52R1289E22-b6b) ? byte control by dqmb ? refresh cycles: 8192 refresh cycles/64 ms ? 2 variations of refresh auto refresh self refresh ordering information pin arrangement type no. frequency ce latency package contact pad HB52R1289E22-a6b 100 mhz 3/4 168-pin dual lead out socket type gold HB52R1289E22-b6b 100 mhz 4 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin
HB52R1289E22-a6b/b6b 3 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3dq145s2 87 dq33 129 s3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v cc 48 nc 90 v cc 132 nc 7dq449v cc 91 dq36 133 v cc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13dq955dq1697dq41139dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v cc 101 dq45 143 v cc 18 v cc 60 dq20 102 v cc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 nc 105 cb4 147 rege 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v cc 68 v ss 110 v cc 152 v ss 27 w 69 dq24 111 ce 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0 72 dq27 114 s1 156 dq59 31 nc 73 v cc 115 re 157 v cc 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63
HB52R1289E22-a6b/b6b 4 pin description note: 1. rege is the register enable pin which permits the dimm to operate in buffered mode and registered mode. to conform to this specification, mother boards must pull this pin to high state (registerd mode). pin no. pin name pin no. pin name pin no. pin name pin no. pin name 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 (ap) 80 nc 122 ba0 164 nc 39 ba1 81 wp 123 a11 165 sa0 40 v cc 82 sda 124 v cc 166 sa1 41 v cc 83 scl 125 ck1 167 sa2 42 ck0 84 v cc 126 a12 168 v cc pin name function a0 to\~a12 address input row addressa0 to a12 column addressa0 to a9, a11 ba0/ba1 bank select addressba0/ba1 dq0 to dq63 data input/output cb0 to cb7 check bit (data input/output) s0 to s3 chip select input re row enable (ras) input ce column enable (cas) input w write enable input dqmb0 to dqmb7 byte data mask ck0 to ck3 clock input cke0 clock enable input wp write protect for serial pd rege* 1 register enable sda data input/output for serial pd scl clock input for serial pd sa0 to sa2 serial address input v cc primary positive power supply v ss ground nc no connection
HB52R1289E22-a6b/b6b 5 serial pd matrix* 1 byte no. function described bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex val- ue comments 0 number of bytes used by module manufacturer 1000000080 128 1 total spd memory size 0000100008 256 byte 2 memory type 0000010004 sdram 3 number of row addresses bits 0 0 0 0 1 1 0 1 0d 13 4 number of column addresses bits 000010110b 11 5 number of banks 0 0 0 0 0 0 1 0 02 2 6 module data width 0 1 0 0 1 0 0 0 48 72 bit 7 module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+) 8 module interface signal levels 0 0 0 0 0 0 0 1 01 lvttl 9 sdram cycle time (highest ce latency) 10 ns 10100000a0 cl = 3 10 sdram access from clock (highest ce latency) 6 ns 0110000060 * 3 11 module configuration type 0 0 0 0 0 0 1 0 02 ecc 12 refresh rate/type 1000001082 normal (7.8125 m s) self refresh 13 sdram width 0 0 0 0 0 1 0 0 04 64m 4 14 error checking sdram width 0 0 0 0 0 1 0 0 04 4 15 sdram device attributes: minimum clock delay for back- to-back random column addresses 0000000101 1 clk 16 sdram device attributes: burst lengths supported 000011110f 1, 2, 4, 8 17 sdram device attributes: number of banks on sdram device 0000010004 4 18 sdram device attributes: ce latency (-a6b) 0000011006 2/3 (-b6b) 0 0 0 0 0 1 0 0 04 3 19 sdram device attributes: s latency 0000000101 0
HB52R1289E22-a6b/b6b 6 byte no. function described bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex val- ue comments 20 sdram device attributes: w latency 0000000101 0 21 sdram device attributes 0 0 0 1 0 1 1 0 16 registered 22 sdram device attributes: general 000011100e v cc 10% 23 sdram cycle time (2nd highest ce latency) (-a6b) 10 ns 10100000a0 cl = 2 (-b6b) undefined 0 0 0 0 0 0 0 0 00 24 sdram access from clock (2nd highest ce latency) (-a6b) 6 ns 0110000060 (-b6b) undefined 0 0 0 0 0 0 0 0 00 25 sdram cycle time (3rd highest ce latency) undefined 0000000000 26 sdram access from clock (3rd highest ce latency) undefined 0000000000 27 minimum row precharge time0001010014 20 ns 28 row active to row active min 0 0 0 1 0 1 0 0 14 20 ns 29 re to ce delay min 0001010014 20 ns 30 minimum re pulse width 0 0 1 1 0 0 1 0 32 50 ns 31 density of each bank on module 1 0 0 0 0 0 0 0 80 2 bank 512m byte 32 address and command signal input setup time 0010000020 2 ns* 3 33 address and command signal input hold time 0001000010 1 ns* 3 34 data signal input setup time 0 0 1 0 0 0 0 0 20 2 ns* 3 35 data signal input hold time 0 0 0 1 0 0 0 0 10 1 ns* 3 36 to 61 superset information 0 0 0 0 0 0 0 0 00 future use 62 spd data revision code 0001001012 rev. 1.2a 63 checksum for bytes 0 to 62 (-a6b) 000110111b 27 (-b6b) 0 0 0 1 1 0 0 1 19 25 64 manufacturers jedec id code0000011107 hitachi 65 to 71 manufacturers jedec id code 0 0 0 0 0 0 0 0 00 72 manufacturing location * 4 (ascii- 8bit code)
HB52R1289E22-a6b/b6b 7 notes: 1. all serial pd data are not protected. 0: serial data, driven low, 1: serial data, driven high these spd are based on intel specification (rev.1.2a). 2.regarding byte32 to 35, based on jedec committee ballot jc42.5-97-119. 3.byte10, 23, 24, 32 through 35 are component spec. 4.byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows j on ascii code.) 5.regarding byte93 and 94, based on jedec committee ballot jc42.5-97-135. bcd is binary coded decimal. 6.all bits of 99 through 125 are not defined (1 or 0). 7.bytes 95 through 98 are assembly serial number. byte no. function described bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex val- ue comments 73 manufacturers part number 0 1 0 0 1 0 0 0 48 h 74 manufacturers part number 0 1 0 0 0 0 1 0 42 b 75 manufacturers part number 0 0 1 1 0 1 0 1 35 5 76 manufacturers part number 0 0 1 1 0 0 1 0 32 2 77 manufacturers part number 0 1 0 1 0 0 1 0 52 r 78 manufacturers part number 0 0 1 1 0 0 0 1 31 1 79 manufacturers part 0 0 1 1 0 0 1 0 32 2 80 manufacturers part number 0 0 1 1 1 0 0 0 38 8 81 manufacturers part number 0 0 1 1 1 0 0 1 39 9 82 manufacturers part number 0 1 0 0 0 1 0 1 45 e 83 manufacturers part number 0 0 1 1 0 0 1 0 32 2 84 manufacturers part number 0 0 1 1 0 0 1 0 32 2 85 manufactures part number 0 0 1 0 1 1 0 1 2d 86 manufacturers part number (-a6b) 0100000141 a (-b6b) 0 1 0 0 0 0 1 0 42 b 87 manufacturers part number 0 0 1 1 0 1 1 0 36 6 88 manufacturers part number 0 1 0 0 0 0 1 0 42 b 89 manufacturers part number 0 0 1 0 0 0 0 0 20 (space) 90 manufacturers part number 0 0 1 0 0 0 0 0 20 (space) 91 revision code 0 0 1 1 0 0 0 0 30 initial 92 revision code 0 0 1 0 0 0 0 0 20 (space) 93 manufacturing date year code (bcd)* 5 94 manufacturing date week code (bcd) * 5 95 to 98 assembly serial number * 7 99 to 125 manufacturer specific data * 6 126 intel specification frequency 0 1 1 0 0 1 0 0 64 100 mhz 127 intel specification ce # latency support (-a6b) 1000011187 cl = 2/3 (-b6b) 1000010185 cl = 3
HB52R1289E22-a6b/b6b 8 block diagram i/o0 to i/o3 dqmb dq0 to dq3 * d0 to d35: hm5225405 pll: 2510 register: 162835 u0: 2-kbit eeprom v cc (d0 to d35, u0) v ss (d0 to d35, u0) v ss v cc notes: 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve "high" state. 4 10 0.0022 f 26 pcs 0.22 f 19 pcs rs1 rs0 cs d0 rdqmb0 i/o0 to i/o3 dqmb dq4 to dq7 4 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 cs d1 i/o0 to i/o3 dqmb dq8 to dq11 4 cs d2 rdqmb1 i/o0 to i/o3 dqmb dq12 to dq15 4 cs d3 i/o0 to i/o3 dqmb cb0 to cb3 4 cs d4 i/o0 to i/o3 dqmb dq32 to dq35 4 cs d9 rdqmb4 i/o0 to i/o3 dqmb dq36 to dq39 4 cs d10 i/o0 to i/o3 dqmb dq40 to dq43 4 cs d11 rdqmb5 i/o0 to i/o3 dqmb dq44 to dq47 4 cs d12 i/o0 to i/o3 dqmb cb4 to cb7 4 cs d13 i/o0 to i/o3 dqmb dq16 to dq19 4 rs3 rs2 cs d5 rdqmb2 i/o0 to i/o3 dqmb dq20 to dq23 4 cs d6 i/o0 to i/o3 dqmb dq24 to dq27 4 cs d7 rdqmb3 i/o0 to i/o3 dqmb dq28 to dq31 4 cs d8 i/o0 to i/o3 dqmb cs d18 i/o0 to i/o3 dqmb cs d19 i/o0 to i/o3 dqmb cs d20 i/o0 to i/o3 dqmb cs d21 i/o0 to i/o3 dqmb cs d22 i/o0 to i/o3 dqmb cs d23 i/o0 to i/o3 dqmb cs d24 i/o0 to i/o3 dqmb cs d25 i/o0 to i/o3 dqmb cs d26 i/o0 to i/o3 dqmb cs d27 i/o0 to i/o3 dqmb cs d28 i/o0 to i/o3 dqmb cs d29 i/o0 to i/o3 dqmb cs d30 i/o0 to i/o3 dqmb cs d31 i/o0 to i/o3 dqmb cs d32 i/o0 to i/o3 dqmb cs d33 i/o0 to i/o3 dqmb cs d34 i/o0 to i/o3 dqmb cs d35 i/o0 to i/o3 dqmb dq48 to dq51 4 cs d14 rdqmb6 i/o0 to i/o3 dqmb dq52 to dq55 4 cs d15 i/o0 to i/o3 dqmb dq56 to dq59 4 cs d16 rdqmb7 i/o0 to i/o3 dqmb dq60 to dq63 4 cs d17 s0 , s1 , s2 , s3 dqmb0 to dqmb7 ba0 to ba1 a0 to a12 re ce cke0 w rs0 , rs1 , rs2 , rs3 rdqmb0 to rdqmb7 rba0 to rba1 -> ba0 to ba1: sdrams d0 to d35 ra0 to ra12 -> a0 to a12: sdrams d0 to d35 rras -> ras : sdrams d0 to d35 rcas -> cas : sdrams d0 to d35 rcke0 -> cke: sdrams d0 to d35 rw -> we : sdrams d0 to d35 r e g i s t e r v cc rege pll ck r1 : sdrams (d0 to d35) register ck0 r2 to r4 12 pf 12 pf v ss ck1 to ck3 10k serial pd sda wp 47 k a0 a1 a2 sa0 sa1 sa2 v ss scl u0 sda scl ck pll
HB52R1289E22-a6b/b6b 9 absolute maximum ratings note: 1.respect to v ss dc operating conditions (ta = 0 to +55 c) notes: 1.all voltage referred to v ss 2.the supply voltage with all vcc and v cc q pins must be on the same level. 3.the supply voltage with all vss and v ss q pins must be on the same level. 4.v ih (max) = v cc + 2.0 v for pulse width 3 ns at v cc . 5.v il (min) = v ss C 2.0 v for pulse width 3 ns at v ss . v il /v ih clamp (component characteristics) this sdram component has v il and v ih clamp for ck, cke, s , dqmb and dq pins. parameter symbol value unit note voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( 4.6 (max)) v 1 supply voltage relative to v ss v cc C0.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 18.0 w operating temperature topr 0 to +55 c storage temperature tstg C50 to +100 c parameter symbol min max unit notes supply voltage v cc 3.0 3.6 v 1, 2 v ss 00v3 input high voltage v ih 2.0 v cc v1, 4 input low voltage v il 0 0.8 v 1, 5 ambient illuminance 100 lx
HB52R1289E22-a6b/b6b 10 minimum v il clamp current minimum v ih clamp current (referred to v ih ) v il (v) i (ma) C2 C32 C1.8 C25 C1.6 C19 C1.4 C13 C1.2 C8 C1 C4 C0.9 C2 C0.8 C0.6 C0.6 0 C0.4 0 C0.2 0 00 v ih (v) i (ma) v cc + 2 10 v cc + 1.8 8 v cc + 1.6 5.5 v cc + 1.4 3.5 v cc + 1.2 1.5 v cc + 1 0.3 v cc + 0.8 0 v cc + 0.6 0 v cc + 0.4 0 v cc + 0.2 0 v cc + 0 0 v il (v) i (ma) ?.5 ? ?.5 ? ?5 ?0 ?5 ?0 ?0 0 ?5 ? 0
HB52R1289E22-a6b/b6b 11 i ol /i oh characteristics (component characteristics) output low current (i ol ) i ol i ol vout (v) min (ma) max (ma) 00 0 0.4 27 71 0.65 41 108 0.85 51 134 1 58 151 1.4 70 188 1.5 72 194 1.65 75 203 1.8 77 209 1.95 77 212 3 80 220 3.45 81 223 v ih (v) v cc + 0 v cc + 1 v cc + 2 v cc + 0.5 v cc + 1.5 i (ma) 8 4 6 0 2 10
HB52R1289E22-a6b/b6b 12 output high current (i oh ) (ta = 0 to 55 c, v cc = 3.0 v to 3.45 v, v ss = 0 v) i oh i oh vout (v) min (ma) max (ma) 3.45 C3 3.3 C28 3 0 C75 2.6 C21 C130 2.4 C34 C154 2 C59 C197 1.8 C67 C227 1.65 C73 C248 1.5 C78 C270 1.4 C81 C285 1 C89 C345 0 C93 C503 i ol (ma) vout (v) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 min max
HB52R1289E22-a6b/b6b 13 i oh (ma) vout (v) 0 ?00 ?00 ?00 ?00 ?00 ?00 0.5 1 1.5 2 2.5 3 min max 3.5 0
HB52R1289E22-a6b/b6b 14 dc characteristics (ta = 0 to 55 c, v cc = 3.3 v 0.3 v, v ss = 0 v) notes: 1.i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2.one bank operation. 3.input signals are changed once per one clock. 4.input signals are changed once per two clocks. 5.input signals are changed once per four clocks. 6.after power down mode, ck operating current. 7.after power down mode, no ck operating current. 8.after self refresh mode set, self refresh current. HB52R1289E22 -a6b -b6b parameter symbol min max min max unit test conditions notes operating current (ce latency = 3) (ce latency = 4) i cc1 2945 ma burst length = 1 t rc = min 1, 2, 3 i cc1 2945 2945 ma standby current in power down i cc2p 803 803 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 767 767 ma cke = v il , t ck = 7 standby current in non power down i cc2n 1415 1415 ma cke, s = v ih , t ck = 12 ns 4 active standby current in power down i cc3p 839 839 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in non power down i cc3n 1775 1775 ma cke, s = v ih , t ck = 12 ns 1, 2, 4 burst operating current (ce latency = 3) i cc4 2945 ma t ck = min, bl = 4 1, 2, 5 (ce latency = 4) i cc4 2945 2945 ma refresh current (ce latency = 3) i cc5 5195 ma t rc = min 3 (ce latency = 4) i cc5 5195 5195 ma self refresh current i cc6 803 803 ma v ih 3 v cc C 0.2 v v il 0.2 v 8 input leakage current i li C10 10 C10 10 m a0 vin v cc output leakage current i lo C10 10 C10 10 m a0 vout v cc dq = disable output high voltage v oh 2.4 2.4 v i oh = C4 ma output low voltage v ol 0.4 0.4 v i ol = 4 ma
HB52R1289E22-a6b/b6b 15 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) notes: 1.capacitance measured with boonton meter or effective capacitance measuring method. 2.measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3.dqmb = v ih to disable data-out. 4.this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 55 c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol max unit notes input capacitance (address) c i1 25 pf 1, 2, 4 input capacitance (re , ce , w )c i2 25 pf 1, 2, 4 input capacitance (cke) c i3 45 pf 1, 2, 4 input capacitance (s )c i4 20 pf 1, 2, 4 input capacitance (ck) c i5 45 pf 1, 2, 4 input capacitance (dqmb) c i6 20 pf 1, 2, 4 input/output capacitance (dq) c i/o1 25 pf 1, 2, 3, 4 HB52R1289E22 -a6b/b6b parameter hitachi- symbol pc100 symbol min max unit notes system clock cycle time (ce latency = 3) t ck tclk 10 ns1 (ce latency = 4) t ck tclk 10 ns ck high pulse width t ckh tch 4 ns 1 ck low pulse width t ckl tcl 4 ns 1 access time from ck (ce latency = 3) t ac tac 7.5 ns 1, 2 (ce latency = 4) t ac tac 7.5 ns data-out hold time t oh toh 2.1 ns 1, 2 ck to data-out low impedance t lz 1.1 ns 1, 2, 3 ck to data-out high impedance t hz 7.5ns1, 4 data-in setup time t ds tsi 2.9 ns 1 data in hold time t dh thi 3.4 ns 1 address setup time t as tsi 2.6 ns 1 address hold time t ah thi 3.0 ns 1, 5 cke setup time t ces tsi 2.6 ns 1, 5 cke setup time for power down exit t cesp tpde 2.6 ns 1
HB52R1289E22-a6b/b6b 16 ac characteristics (ta = 0 to 55 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (cont) notes: 1.ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.5 v. 2.access time is measured at 1.5 v. load condition is c l = 50 pf. 3.t lz (max) defines the time at which the outputs achieves the low impedance state. 4.t hz (max) defines the time at which the outputs achieves the high impedance state. 5.t ces defines cke setup time to ck rising edge except power down exit command. test conditions ? input and output timing reference levels: 1.5 v ? input waveform and output load: see following figures ? ambient illuminance: under 100 lx ? HB52R1289E22 -a6b/b6b parameter hitachi- symbol pc100 symbol min max unit notes cke hold time t ceh thi 3.0 ns1 command setup time t cs tsi 2.6 ns 1 command hold time t ch thi 3.0 ns 1 ref/active to ref/active command period t rc trc 70 ns 1 active to precharge command period t ras tras 50 120000 ns 1 active command to column command (same bank) t rcd trcd 20 ns 1 precharge to active command period t rp trp 20 ns 1 write recovery or data-in to precharge lead time t dpl tdpl 20 ns 1 active (a) to active (b) command period t rrd trrd 20 ns 1 transition time (rise to fall) t t 15ns refresh period t ref 64ms t t 2.4 v 0.4 v 0.8 v 2.0 v input t t dq cl
HB52R1289E22-a6b/b6b 17 relationship between frequency and minimum latency parameter HB52R1289E22 frequency (mhz) -a6b/b6b t ck (ns) hita- chi symbol pc100 symbol 10 notes active command to column command (same bank) i rcd 21 active command to active command (same bank) i rc 7= [i ras + i rp ] 1 active command to precharge command (same bank) i ras 51 precharge command to active command (same bank) i rp 21 write recovery or data-in to precharge command (same bank) i dpl tdpl 2 1 active command to active command (different bank) i rrd 21 self refresh exit time i srex tsrx 2 2 last data in to active command (auto precharge, same bank) i apw tdal 4 = [i dpl + i rp ] self refresh exit to command input i sec 7= [i rc ] 3 precharge command to high impedance (ce latency = 3) i hzp troh 3 (ce latency = 4) i hzp troh 4 last data out to active command (auto precharge) (same bank) i apr 0 last data out to precharge (early precharge) (ce latency = 3) i ep C2 (ce latency = 4) i ep C3 column command to column command i ccd tccd 1 write command to data in latency i wcd tdwd 1 dqmb to data in i did tdqm 1 dqmb to data out i dod tdqz 3 cke to ck disable i cle tcke 2 register set to active command i rsa tmrd 1 s to command disable i cdd 0 power down exit to command input i pec 1 burst stop to output valid data hold (ce latency = 3) i bsr 2 (ce latency = 4) i bsr 3
HB52R1289E22-a6b/b6b 18 notes: 1.i rcd to i rrd are recommended value. 2.be valid [dsel] or [nop] at next command of self refresh exit. 3.except [dsel] and [nop] pin functions ck0 to ck3 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. s0 to s3 (input pin): when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. re , ce and w (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the com- bination of their voltage levels. for details, refer to the command operation section. a0 to a12 (input pins): row address (ax0 to ax12) is determined by a0 to a12 level at the bank active command cycle ck rising edge. column address (ay0 to ay9, ay11) is determined by a0 to a9, a11 level at the read or write command cycle ck rising edge. and this column address becomes burst access start ad- dress. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by ba0/ ba1 (ba) is precharged. ba0/ba1 (input pin): ba0/ba1 are bank select signal (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if ba0 is low and ba1 is low, bank 0 is selected. if ba0 is high and ba1 is low, bank 1 is selected. if ba0 is low and ba1 is high, bank 2 is selected. if ba0 is high and ba1 is high, bank 3 is selected. cke0 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down and clock suspend modes. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z. write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written. dq0 to dq63, cb0 to cb7 (input/output pins): data is input to and output from these pins. v cc (power supply pins): 3.3 v is applied. v ss (power supply pins): ground is connected. parameter HB52R1289E22 frequency (mhz) -a6b/b6b t ck (ns) hita- chi- symbol pc100 symbol 10 notes burst stop to output high impedance (ce latency = 3) i bsh 3 (ce latency = 4) i bsh 4 burst stop to write data ignore i bsw 1
HB52R1289E22-a6b/b6b 19 rege (input pins): if rege is high, the register is registered mode. if rege is low, the register is buffered mode. detailed operaion part refer to the hm5225165b/hm5225805b/hm5225405b-75/a6/b6 datasheet. physical outline 3.00 133.37 0.118 5.251 127.35 5.014 3.00 0.118 8.89 11.43 36.83 54.61 0.350 0.450 2.150 1.450 a b c 1 84 front side back side 1.27 0.10 4.00 min 0.157 min 0.050 0.004 4.80 0.189 85 4.00 0.157 17.80 0.700 38.10 1.500 168 2 e f 3.00 2 ? f 0.118 component area (front) component area (back) 6.35 0.250 3.175 0.125 detail b detail a 0.20 0.15 2.50 0.20 0.008 0.006 0.098 0.008 3.125 0.125 0.123 0.005 1.27 0.050 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 6.35 0.250 4.175 0.164 detail c 3.125 0.125 0.123 0.005 2.00 0.10 0.079 0.004 unit: mm inch note: tolerance on all dimensions 0.15/0.006 unless otherwise specified. full r full r
HB52R1289E22-a6b/b6b 20 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copy- right, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have re- ceived the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, con- tact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or fail- ure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equip- ment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor prod- ucts. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
HB52R1289E22-a6b/b6b 21 revision record rev. date contents of modification drawn by approved by 0.0 jul. 14, 1999 initial issue (referred to hm5225165b/hm5225805b/hm5225405b- 75/a6/b6 rev.0.0)

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